The present invention is directed to the construction and manufacture of semiconductor capacitively coupled negative differential resistance (xe2x80x9cNDRxe2x80x9d) devices, and to circuit applications such as SRAMs and power thyristors that include such devices.
The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafers. Integrated circuits of this type are manufactured through a series of steps carried out in a particular order. The main objectives in manufacturing many such devices include obtaining a device that occupies as small an area as possible and consuming low levels of power using low supply levels, while performing at speeds comparable to speeds realized by much larger devices. To obtain these objectives, steps in the manufacturing process are closely controlled to ensure that rigid requirements, for example, of exacting tolerances, quality materials, and clean environment, are realized.
An important part in the circuit construction, and in the manufacture, of semiconductor devices concerns semiconductor memories: the circuitry used to store digital information. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the store information. In applications where circuit space, power consumption, and circuit speed are primary design goals, the construction and layout of current switching devices can be very important.
Conventional random access memory devices, such as SRAM and DRAM, often compromise these primary design goals. SRAMs, for example, include circuit structures that compromise at least one of these primary design goals. A conventional SRAM based on a four-transistor (xe2x80x9c4Txe2x80x9d) cell or a six-transistor (xe2x80x9c6Txe2x80x9d) cell has four cross-coupled transistors or two transistors and two resistors, plus two cell-access transistors. Such cells are compatible with mainstream CMOS technology, consume relatively low levels of standby power, operate at low voltage levels, and perform at relatively high speeds. However, the 4T and 6T cells are conventionally implemented using a large cell area; and this significantly limits the maximum density of such SRAMs.
Other SRAM cell designs are based on NDR (Negative Differential Resistance) devices. They usually consist of at least two active elements, including an NDR device. The NDR device is important to the overall performance of this type of SRAM cell. A variety of NDR devices have been introduced ranging from a simple bipolar transistor to complicated quantum-effect devices. The biggest advantage of the NDR-based cell is the potential of having a cell area smaller than 4T and 6T cells because of the smaller number of active devices and interconnections. Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. Some of these problems include: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for the cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; and manufacturability and yield issues due to complicated fabrication processing.
NDR devices such as thyristors are also widely used in power switching applications because the current densities carried by such devices can be very high in their on state. However, a significant difficulty with these devices in such applications is that once switched to their on-state, they remain in this state until the current is reduced below the device holding current. Also, in general, when the main current is interrupted, the time required for the thyristor to return to the blocking (OFF) state is largely determined by the carrier lifetime and can be quite long. This inability to switch the device off without interrupting the current and the associated slow switching speed are significant problems in many applications and have resulted in many attempts to modify the device structures so that it can be actively and rapidly switched off.
One aspect of the present invention provides a capacitively coupled NDR device and processing implementation that largely alleviates the above-mentioned problems.
According to one example embodiment of the present invention, a semiconductor device includes an NDR device and a control port. The NDR device has at least two contiguous regions of opposite polarity, and the control port is located adjacent to, capactively coupled to and facing at least one of the regions of the NDR device. The one region has a cross-section along a plane facing an interface between two of the contiguous regions, and the control port and the NDR device are configured and arranged so that the capacitive coupling between the gate and said one region changes the potential across a majority of the cross-section in response to at least one voltage transition presented to the control port and independent of any MOS inversion channel formation. This action enhances switching of the NDR device between a current-passing mode and a current-blocking mode.
According to another embodiment of the present invention, a semiconductor device includes an array of memory cells, and an access circuit configured and arranged to provide reading and writing access to one or more selected cells in the array. Each cell has a storage node, a capacitively-switched NDR device configured and arranged to enhance writing to the storage node, and a data circuit configured and arranged to couple data to the storage node and the access circuit.
According to yet another embodiment of the present invention, a semiconductor device includes a power switch structure. The power switch structure includes a plurality of combination NDR-device and control-port circuits. Each NDR device has at least two contiguous regions of opposite polarity, and the associated control port is located adjacent to capacitively coupled to and facing at least one of the regions of the NDR device. The one region has a cross-section along a plane facing an interface between two of the contiguous regions, and the control port and the NDR device are configured and arranged so that the potential across the entire cross-section changes in response to a control voltage presented to the control port.
The above summary of the present invention is not intended to characterize each disclosed embodiment of the present invention. Among various other aspects contemplated as being within the scope of the claims, the present invention is also directed to methods of manufacturing the above structures and their respective circuit layouts.